Arm Builtin · Indexed 2026-07-11

Senior IP Design Engineer

Remote / flexible 162K-219K Annually

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Indexed description

Arm Senior IP Design Engineer YesterdaySaved Hybrid 2 Locations 162K-219K Annually Senior level 162K-219K Annually Senior levelArtificial Intelligence • Internet of Things • SemiconductorDesign and develop reconfigurable Fuse and JTAG subsystems: write and debug RTL (SystemVerilog), perform static checks and implementation constraints, ensure quality and manufacturability across SoCs, collaborate with verification on test plans and debugging, and drive Arm-recommended solutions.Top Skills: Analog Ip IntegrationArmBmodsCdcClock Domain CrossingDftFuseJtagLintingOccOtpPerlPower Domain CrossingPythonRdcRtlScan InsertionSocSystemverilogTapX-Propagation

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Arm Company profile preview

Source: Builtin
Location: Remote / flexible
Compensation: 162K-219K Annually
Open on Caio: 123 roles

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162K-219K Annually

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123open roles 2sources 9markets Posted 2d agolatest role