Coherent Fabric Design

Arm Coherent Fabric Design YesterdaySaved Hybrid Austin, TX, USA 198K-268K Annually Senior level 198K-268K Annually Senior levelArtificial Intelligence • Internet of Things • SemiconductorDesign RTL logic for a coherent interconnect fabric using SystemVerilog. Collaborate with verification, implementation, performance, and power teams to deliver high-performance, low-power IP. Track and coordinate tasks, debug functional and performance issues with simulation and tools, and improve design methodology across the System IP group.Top Skills: Amba ChiAxiDdrDftEthernetLintMakefilesPci Express (Pcie)PerlPhysical DesignRubyShellStatic Timing AnalysisSynthesisSystemverilogUnix/Linux