silicon validation - Silicon Validation, UVM, SystemVerilog

Silicon Validation Engineer

Position Overview
We are seeking a Silicon Validation Engineer to plan and execute validation of ASIC/SoC devices from pre-silicon RTL validation through silicon bring-up. The role owns test plan creation, testbench and regression development, lab and board bring-up, debug and root-cause analysis, and cross-functional coordination with firmware, design, DFT and system teams to ensure silicon meets functional, electrical, timing and protocol requirements. The ideal candidate has strong mixed-signal/RTL validation experience, hands-on lab and emulation skills, and a proven track record of finding and closing complex silicon issues.

Key Responsibilities

• Develop and execute comprehensive silicon validation plans covering functional, protocol, electrical and performance requirements.
• Design and maintain UVM/SystemVerilog testbenches, constrained-random tests, functional coverage models, and coverage-driven verification flows.
• Create, run and maintain automated regression environments (simulation, emulation and hardware) and analyze results to detect and debug failures.
• Perform pre-silicon RTL validation and SVA-based assertion verification; generate and analyze coverage reports to drive closure.
• Lead silicon bring-up activities: board bring-up, FPGA prototyping, power-up sequencing, firmware bring-up (U-Boot/Linux), and initial system bring-up in the lab.
• Use emulation (Palladium, Veloce, ZeBu), gate-level simulation and SDF back-annotation to validate timing-dependent behavior and hard-to-simulate scenarios.
• Develop and execute targeted silicon stress tests for protocols (AXI, PCIe, DDR/LPDDR/HBM, Ethernet, USB, UART, JESD204, MIPI, SATA, I2C, SPI, AMBA) and system scenarios.
• Perform lab debug using protocol analyzers, logic analyzers, oscilloscopes, boundary-scan and other hardware debug tools; reproduce failures and drive root cause to design/firmware/test teams.
• Integrate and validate firmware and drivers; use SystemVerilog DPI, C/C++ and scripting to create test harnesses and automate bring-up procedures.
• Work with DFT, ATPG, BIST, scan and equivalence checking teams to validate testability and support failure analysis and production testing.
• Collaborate with timing and physical teams on Static Timing Analysis (PrimeTime) issues, power/clock gating interactions, and CDC/metastability analyses.
• Maintain bug tracking (JIRA) and reporting processes; document test plans, procedure, silicon errata and verification closure evidence.
• Mentor junior engineers, coordinate cross-functional validation activities, and contribute to continuous improvements in tools and flows.

Qualifications

• B.S./M.S. in Electrical Engineering, Computer Engineering or related field (or equivalent experience).
• 5+ years of silicon/ASIC validation, SoC bring-up or related verification experience (senior level adjust as needed).
• Strong verification skills with UVM, SystemVerilog, constrained-random verification, functional coverage and scoreboards.
• Hands-on experience with RTL validation, Verilog, SystemVerilog Assertions (SVA), simulation tools (VCS, Questa, Xcelium, ModelSim) and gate-level simulation.
• Experience with emulation platforms (Palladium, Veloce, ZeBu) and FPGA prototyping on Xilinx or Intel/Altera families.
• Familiarity with Static Timing Analysis (PrimeTime), SDF back-annotation and timing closure issues.
• Experience with SOC validation, bootloader/firmware bring-up (U-Boot), Linux kernel/device driver debug and SystemVerilog DPI or C/C++ integration.
• Proficient in lab bring-up and debug using protocol analyzers, logic analyzers, oscilloscopes, boundary-scan, JTAG and board bring-up procedures.
• Knowledge of protocols such as AXI, PCIe, DDR/LPDDR/HBM, Ethernet, USB, UART, JESD204, MIPI, SATA, I2C and SPI.
• Experience with linting tools (SpyGlass), formal verification tools (JasperGold, OneSpin), equivalence checking and CDC/metastability analysis is a plus.
• Scripting and automation skills: Python, TCL, Perl, shell scripting and experience with regression automation tools (Jenkins).
• Familiarity with power/clock gating design, low-power verification flows, and electrical/parametric testing concepts.
• Experience with debug/view tools (Verdi, DVE), scoreboards, test harness development, and failure analysis.
• Knowledge of DFT/scan test, ATPG, BIST, silicon bring-up and production test flows and working with JIRA for bug tracking.

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Kameshwara Sai - Consultant

For this position, you must be currently authorized to work in the United States without the need for sponsorship for a non-immigrant visa. This is a new role.

This job was first posted by CyberCoders on 09/02/2026 and applications will be accepted on an ongoing basis until the position is filled or closed.

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