Senior IP Design Engineer

MediaTek is a leading global fabless semiconductor company powering more than 2 billion devices a year. Our cutting-edge system-on-chip solutions enable some of the world’s most popular smartphones, smart TVs, connectivity products, IoT devices, and more. We combine deep engineering expertise with a collaborative, fast-paced work environment where innovation, curiosity, and teamwork drive everything we do. About the Role MediaTek is seeking a motivated Senior IP Design Engineer interested in architectural modeling and digital design for Dynamic Voltage & Frequency Scaling (DVFS) IP. In this role, you will build high-level architectural models for DVFS IP to evaluate new architectures and features; identify system-level performance bottlenecks and explore design trade-offs; develop quality digital designs using SystemVerilog RTL based on architectural specifications; conduct RTL signoff checks and collaborate with physical design teams on performance optimization. You will gain the opportunity to develop state-of-the-art power and performance management used in High-Performance Compute (HPC) products, including the design of clock delivery networks (CDN) and power delivery networks (PDN) for modern CPU/GPU/NPU. Key Responsibilities 1. Architectural Modeling: Build high-level architectural models to evaluate new architectures, features, and design trade-offs before RTL implementation. 2. Digital Design Development: Create quality digital designs using SystemVerilog RTL that meet the computational functions or control sequences specified in the design specifications. 3. Conduct RTL sign-off checks, including LINT, CDC, & CLP. 4. Co-work with verification teams for block-level and system-level verification 5. Supply necessary collateral for physical design, including SDC/UPF, and collaborate with the physical design team for timing critical path and power analysis.

Main Requirements and Qualifications

• Educational Background: Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or a related field, or equivalent experience.
• Industrial Experience: 5+ years of working experience in RTL design
• Digital Design Knowledge: Working knowledge of digital circuit design including but not limited to FSM, register file, memory system, bus handshake protocol, and algorithmic logic unit.
• Architectural Modeling and RTL Coding Skill: Proficiency in SystemVerilog coding is required, along with working knowledge of design synthesis, power, performance, and area trade-offs.
• Communication and Teamwork: Strong communication, presentation, and teamwork skills.
• EDA Tool Proficiency: Familiarity with industry-standard EDA tools for RTL design simulation and quality check flows.
• Scripting Languages: Knowledge of coding agents like Claude is a plus
• Location: Austin, TX (preferred) or San Diego, CA
• Hybrid working schedule: Monday to Thursday work on-site, and Friday work from home.

Salary range: $128,600-$203,600 (depends on the location)

• Employee may be eligible for performance bonus, short- and long-term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Sick Leave, Vacation time, Parental leave, 401K and more.

• MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation.