Back to search
UST Linkedin · Posted 18d ago

Associate III - VLSI SDC Design Engineer

India

Linkedin
Continue to application Add your email once, then Caio opens the original posting.

Indexed description

Role Description

Job description: Std cells Person having 3+ years experience in standard cell design and verification. He / she should be having sound knowledge of different types of standard cells (Combinational, sequential Level shifters etc) and verifications of the same. He / She should be able to benchmark different standard cells for PPA. Awareness of digital flow will be a plus. Person is supposed to work with and guide other junior members in design and layout domain.

Skills

vlsi design,benchmarking,cell design,digiteal,

Free. 20 seconds. No password. See every match in this search.

Create a free Caio profile to unlock more results and save your role and location preferences.

Unlock free search
Want help applying to roles like this? Search Caio for free. If repetitive applications get heavy, Managed Job Search adds supervised execution for $99/month.
View Managed Job Search