Lead ASIC Design Engineer

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MITRE’s Electronic Systems Development Department is seeking exceptional ASIC engineers to help solve some of the nation’s most challenging technical problems. Our engineers work at the forefront of microelectronics innovation, developing advanced prototypes and proof-of-concept systems that directly support national security and critical government missions.

As part of a highly collaborative, multidisciplinary team, you will contribute to groundbreaking research and development efforts spanning advanced semiconductor technologies, embedded systems, communications, sensing, and signal processing. Our diverse sponsor portfolio provides exposure to a broad range of impactful technical challenges, including:

• Development of next-generation prototypes leveraging advanced semiconductor process nodes
• Highly integrated, low Size, Weight, Power, and Cost (SWaP-C) platforms for mission-critical applications
• Real-time communication, sensing, and navigation systems utilizing cutting-edge FPGA and Software Defined Radio (SDR) technologies
• Advanced architectures for high-throughput signal processing and embedded computing
• Collaboration with world-class engineers and researchers on projects of national importance

Roles & Responsibilities:

Our team specializes in the rapid design, development, and deployment of advanced embedded systems for sensing, communications, and navigation applications. In this role, you will have the opportunity to:

• Architect and develop highly integrated, low-SWaP-C ASIC and FPGA solutions
• Lead the design, integration, bring-up, and testing of custom hardware prototypes
• Drive development efforts across both ASIC and FPGA technologies throughout the design lifecycle, including requirements definition, architecture, design, verification, testing, and concept demonstration
• Implement and optimize advanced algorithms in hardware and software on embedded platforms
• Lead project teams and mentor junior engineers
• Interface with sponsors and build relationships for future programs and task
• Evaluate and incorporate emerging technologies into next-generation prototype systems

Basic Qualifications:

Typically requires a minimum of 8 years of related experience with a Bachelor’s degree in electrical engineering, computer engineering, or a related field or 6 years and a Master’s degree in electrical engineering, computer engineering, or a related field

Experience in one or more RTL languages, including VHDL, Verilog, and/or SystemVerilog

Experience leading RTL design, simulation, synthesis, timing closure, and verification methodologies

Demonstrated hands-on experience with EDA tool suites from industry leaders such as Cadence, Synopsys, and Siemens

Experience designing and deploying ASICs on advanced semiconductor process nodes (

Experience developing and integrating complex embedded hardware systems

Deep understanding and application of best practices for design, verification, test, and deployment

Experience integrating third-party IP into ASICs

Proficiency with scripting and automation tools such as Python, TCL, CMake, or similar

Experience leading technical efforts and small engineering teams

Excellent written and verbal communication skills

Experience working with semiconductor fabrication partners, EDA vendors, and third-party IP providers and integrating their solutions into a design flow

Must be eligible to obtain and maintain a Top Secret U.S Government issued Security Clearance. Per the U.S. Government’s eligibility requirements, you must be a U.S Citizen to be considered for a security clearance.

This position requires a minimum of 4 days a week on-site

Preferred Qualifications:

Active Secret or Top Secret clearance.

Experience working directly with sponsors and managing project execution within national security programs

Experience with leading-edge semiconductor technologies (

Experience with Design for Manufacturing (DFM) challenges, rules, methods, and validation workflows

Expertise spanning the complete digital design lifecycle, including architecture, implementation, verification, testing, documentation, and configuration management

Strong understanding of processor interfaces, memory-mapped architectures, and interrupt-driven systems

Deep knowledge of microelectronics, digital circuits, and transistor-level design concepts

Demonstrated leadership in FPGA verification methodologies, including UVM and OVM

Experience with hardware emulation platforms such as Cadence Palladium and Siemens Veloce

This requisition requires the candidate to have a minimum of the following clearance(s):

None

This requisition requires the hired candidate to have or obtain, within one year from the date of hire, the following clearance(s):

Top Secret

Salary compensation range and midpoint:

$156,400 - $195,500 - $234,600 Annual

Work Location Type:

Onsite

It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.

Commitment to Non-Discrimination

All qualified applicants will receive consideration for employment without regard to disability, status as a protected veteran or any other status protected by applicable federal, state, local or international law.

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