CPU Implementation Methodology Engineer

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products!

Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation.

Description

• Generate and validate new ideas, create flows and methodologies around them by working with CPU Designers, CAD teams and EDA tool vendors to improve PPA

• Detailed analysis across partitions to understand optimization opportunities

• Cross functional collaboration across STA, library, tech and post silicon teams to improve optimization during Implementation

• Contribute to aspects of Synthesis and Physical Design Implementation methodologies

Preferred Qualifications

Experience implementing high-performance and low-power CPU designs

Scripting skills to interface with tools and analyze data

Experience with SAPR/PNR design flow infrastructure/scripts

Proficiency in programming and scripting (Example: Python, TCL)

Understanding of challenges related to latest deep sub-micron technology and ability to write algorithms and code to extract PPA during Implementation

Strong interpersonal skills and ability to work effectively in a dynamic team environment

Strong understanding and experience using industry standard synthesis, PnR, and STA tools

Excellent debugging and problem-solving skills

Minimum Qualifications

Minimum BS and 3+ years of relevant industry experience

Experience with implementing VLSI digital designs using SAPR tools with multi-GHz performance goals

Experience with logic optimization trade-offs between area, timing and power