RTL Design Engineer - Memory Controller

Arm RTL Design Engineer - Memory Controller YesterdaySaved Hybrid Austin, TX, USA 198K-268K Annually Senior level 198K-268K Annually Senior levelArtificial Intelligence • Internet of Things • SemiconductorDesign and implement SystemVerilog RTL for memory controller functional units. Develop specifications and microarchitecture, collaborate with design and verification teams, debug functional and performance issues, and meet performance, power, and area targets. The role requires knowledge of DRAM standards, AMBA bus protocols, RTL design, synthesis, and design-quality checks such as lint and CDC analysis.Top Skills: Amba4 AceAmba5 ChiAxiCdc AnalysisDdr5Ddr6Hbm3Hbm4Logic SynthesisLpddr5Lpddr6Power AnalysisRtl DesignRtl LintSystemverilogVerilogVhdl