Senior Package Layout Engineer

Arm Senior Package Layout Engineer YesterdaySaved Hybrid Chandler, AZ, USA 162K-219K Annually Senior level 162K-219K Annually Senior levelArtificial Intelligence • Internet of Things • SemiconductorDesigns, develops, and verifies IC package layouts for next-generation System-in-Package and SoC products. Responsibilities include high-speed and high-power routing, stack-up creation, reference-plane and power-distribution implementation, feasibility studies, and resolving complex design issues using Cadence APD or SiP tools. The engineer will also improve packaging methodologies, support standardization, evaluate design tradeoffs involving size, cost, and performance, and collaborate with globally distributed teams.Top Skills: 2.5D Packaging3D PackagingCadence AllegroCadence ApdCadence SipEda ToolsHigh-Speed Signal IntegrityIc Package LayoutPower Integrity