Principal PCIe Subsystem Verification Engineer

Arm Principal PCIe Subsystem Verification Engineer Reposted 12 Hours AgoSaved Hybrid Austin, TX, USA 250K-338K Annually Senior level 250K-338K Annually Senior levelArtificial Intelligence • Internet of Things • SemiconductorLead subsystem-level verification of PCIe and CXL IOs: define verification strategy, craft test plans, develop SystemVerilog/Verilog/UVM testbenches, run simulation/emulation, debug issues, improve methodologies, and mentor junior engineers while coordinating with architects and project managers.Top Skills: CodexCxlDebuggersEmulation PlatformsFormal MethodologyGeneric Interrupt Controller (Gic)PciePerlPythonSimulation PlatformsSmmuSystemverilogTransactorsUvmVerilogVerilog Hdl