NPU Architecture Engineer

Who we are

We are a team that designs the architecture and develops software for high-performance AI semiconductors (NPUs) used in autonomous driving and robotics.

We are responsible for architecture and Instruction Set Architecture (ISA) design, deep learning compiler and performance simulator development, as well as architectural optimization through Design Space Exploration (DSE).

Responsibilities

This role is responsible for analyzing deep learning workloads for autonomous driving and robotics, defining hardware and software requirements, and designing NPU architectures and Instruction Set Architectures (ISAs) accordingly.

In this role, you will also develop performance simulators and Design Space Exploration (DSE) environments, leveraging them to analyze bottlenecks and drive architectural optimization.

■ NPU Architecture and ISA Design

• Designing NPU architectures and ISAs that incorporate deep learning workload characteristics
• Design compute architectures, memory hierarchies, and data movement schemes
• Define instruction structures, develop execution scenarios, and write/maintain architecture and ISA specifications

■ NPU Performance Model Development and Verification

• Developing performance models to verify and validate NPU architecture performance
• Design and implement performance models, and establish simulation environments
• Analyze performance bottlenecks, assess design alternatives, and derive directions for performance improvement

■ Deep Learning Workload Analysis and Hardware/Software Requirement Definition

• Defining NPU requirements through analysis of deep learning models and operator characteristics
• Specify interfaces and requirements in collaboration with cross-functional teams (e.g., Deep Learning Compiler, HW (RTL), and Device Driver)
• Review the feasibility of new features and architectural changes, and identify verification items

Minimum Qualifications

• Master's degree in Electrical Engineering, Computer Science, or a related technical field
• Minimum 2 years of experience in AI accelerator, NPU, or GPU architecture design, performance model/simulator development, etc. (a relevant degree may be considered equivalent to professional experience)
• Experience in two or more of the following areas: ISA design and specification development, architecture design/exploration, and performance simulator development
• Experience in hardware architecture design or performance verification through analysis of deep learning models or key operator characteristics
• Experience implementing and validating architectural designs using simulation models
• Experience developing C/C++ simulators, performance models, or system software
• Experience working with Linux development environments and using collaboration tools (e.g., Git, CMake)

Preferred Qualifications

• Ph.D. in Computer Architecture, AI semiconductor (NPU) design, or a related field
• Experience in fabless semiconductor or related companies specializing in AI accelerators (e.g., NPU, GPU)
• Experience in NPU or AI accelerator architecture design, ISA definition, and performance verification
• Experience analyzing and optimizing key deep learning operators (e.g., Conv, GEMM, Attention)
• Experience defining architectural requirements through collaboration with cross-functional teams (e.g., Compiler, RTL, Device Drivers)
• Experience designing hardware architectures and software interfaces from a product development or commercialization perspective
• Experience in SystemC/TLM modeling or simulator development
• Experience using hardware modeling or design automation tools (e.g., Chisel, HLS)
• Experience building analysis, automation, and verification environments using Python
• Proficiency in English (fluent in both written and oral business communication)

Others

[Notes]

• In accordance with the employment protection laws, eligible candidates (disabled individuals, veterans, etc.) will receive preferential benefits during the process.
• Applications are accepted only through the Hyundai Motor Company career page, and any other methods are not allowed.
• The recruitment process may differ based on the timeline of the application submission, and the job post may close early if the position is filled.
• Additional assignments may be given during the interview rounds, if necessary.
• The recruitment schedule may be adjusted depending on the progress of the recruitment process.
• The expected position level specified in the job description may change based on each individual's experience and evaluation results.
• For any inquiries on recruitment, please refer to the [FAQs] or submit a ticket through '1:1 Inquiries' on our webpage.

[Precautions]

• If any of the following conditions apply, your acceptance may be revoked, or you may be subject to disadvantages in the selection process: 
• If the information submitted during the recruitment process (including the application form) differs or cannot be proven in documentation
• If you are ineligible to work under company regulations
• If you are ineligible to travel abroad (for men, Korean nationals who have not completed military service or are not exempt from military service by the joining date)
• If you are unable to join the company on the start date designated by the company upon receiving the final offer
• Our company respects the trade secrets of third parties and strives to comply with relevant laws and regulations, such as The Unfair Competition Prevention and Trade Secret Protection Act. Please be careful not to disclose any confidential information related to your former/current workplace or to violate the confidentiality obligation of your former/current workplace, during the recruitment process. Violation may result in disadvantage in the recruitment process.

Position: Research Engineer, Senior Research Engineer