Principal Design Engineer - High-Speed Interconnect

Arm Principal Design Engineer - High-Speed Interconnect Reposted 11 Hours AgoSaved Hybrid Austin, TX, USA 250K-338K Annually Senior level 250K-338K Annually Senior levelArtificial Intelligence • Internet of Things • SemiconductorLead microarchitecture, RTL development, and integration of high-speed interconnect subsystems (PCIe, CXL, UALink). Translate requirements into synthesizable RTL, collaborate across architecture, verification, firmware, and physical design, analyze traffic and buffering tradeoffs, drive delivery from concept through synthesis and timing closure, mentor engineers, and debug cross-functional issues to meet performance, power, area, and reliability targets.Top Skills: AceApbAxiCdcChiChipletsCxlCxl 2.0Formal VerificationLintPciePcie Gen6PhyRdcRtlSynthesisSystemverilogTiming AnalysisUalinkWaveform DebugX-Propagation