FPGA Design Engineer

Type: full-time, on-site/hybrid (remote options for EU residents)

Experience: Medior, Senior

Tannera is a PHY IP design company founded in 2018, with offices in Belgrade, Serbia and Santa Monica, California. We specialize in 5G NR, O-RAN, and satellite communication systems—building best-in-class algorithms and hardware architectures deployed in next-generation wireless infrastructure worldwide.

We are looking for FPGA Design Engineers across multiple seniority levels to join our PHY development team. You will be responsible for designing, implementing, optimizing, and integrating high-throughput 5G NR signal processing blocks and system architectures on state-of-the-art FPGA platforms.

What You'll Do

Medior & Senior Roles

• Design: Develop RTL (VHDL/Verilog) for complex DSP algorithms tailored for 5G PHY.
• Optimize: Push the limits of FPGA resources to achieve ultra-low latency and maximum throughput.
• Verify: Create unit tests alongside IP core implementation (testbench, FPGA runtime testing), validating in hardware-in-the-loop environments.
• Collaborate: Work closely with our Algorithm team to translate mathematical models (MATLAB/Python) and/or software-level modules (C/C++) into efficient hardware architectures. Work with the rest of the PHY team on the system-level FPGA firmware development and validation.
• Integrate: Work closely with SW teams to integrate FPGA accelerators.

Senior Roles

• Architect: Develop system-level hardware/firmware architecture.
• Mentor: Lead design reviews and guide junior engineers through the nuances of FPGA design and validation.

What We're Looking For

Depending on your level, we expect a mix of the following:

Experience:

• 3+ years of industry experience in digital ASIC/FPGA design

The Fundamentals:

• Proficiency in HDL (VHDL or Verilog)
• Experience in C/C++ and Python
• Familiarity with AMD Versal and/or UltraScale+ platforms
• Experience with FPGA interfacing (PCIe, Ethernet, and other high-speed serial communication)
• Experience with CocoTB, and/or Python-based cosimulation is a plus

The 5G Factor:

• Digital signal processing expertise
• Experience with hardware architectures for DSP and wireless PHY is a huge plus

The Mindset:

• A problem-solver who enjoys design at the bit-level and cares about clean, maintainable code.

Soft-skills:

• We value excellent written and verbal communication, as well as technical presentation skills.

Why Tannera

• Cutting-Edge Tech: At Tannera, we design advanced PHY algorithms and hardware architectures for 5G NR, O-RAN, and satellite communication systems. We work on AMD Versal and Virtex UltraScale+ FPGAs and partner with industry-leading vendors to deploy best-in-class, low-power base station technology.
• Impact: Your code will run in the infrastructure that connects millions.
• Growth: A flat hierarchy where your ideas are heard, and professional development is prioritized.
• Flexibility: We value output over “desk time.” The role is primarily on-site in Belgrade, with hybrid flexibility available after the onboarding period.

How to Apply

Send your CV and a brief note about your most interesting hardware/firmware project to [email protected]. Learn more about Tannera at tannera.io.