Real-Time Developer - Senior Member of Technical Staff (SMTS)

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Project Description:

AMD is building a hardware-assisted security platform that uses silicon-level Performance Monitoring Counters (PMCs) and on-chip machine learning to detect advanced endpoint threats (ransomware, fileless malware, cryptojacking) at the processor layer, below OS-based evasion. The platform collects CPU behavioral telemetry, classifies it via an ML inference engine, and exposes threat signals to security-software partners through a standardized API. The team covers the full stack: silicon telemetry, ML training/validation, real-time inference, lab qualification and CI/CD.

Responsibilities:

• Architect the end-to-end real-time detection pipeline: from kernel PMU driver telemetry collection through GPU/NPU inference to multi-subscriber API delivery.
• Lead the streaming SDK architecture: low-latency threat signal delivery, multi-subscriber support, backpressure management and subscriber isolation.
• Design and own the ISV API specification across product generations, ensuring backward compatibility across platform releases.
• Architect tamper-resistant telemetry collection to ensure the integrity of hardware signals delivered to consumers.
• Define performance budgets for the real-time pipeline; own end-to-end latency and CPU overhead targets across enterprise deployment configurations.
• Lead security-software partner integration architecture reviews and certify integration patterns.
• Mentor and technically guide MTS-level real-time developers; lead architecture and code reviews.
• Contribute to and review API documentation, integration SDKs and published technical specifications.

Mandatory Skills Description:

• Solid experience: systems programming in C and/or C++, with 3+ years on real-time or security-critical systems.
• Expert-level knowledge of low-latency pipeline design: kernel/user-space IPC, memory-mapped I/O, lock-free data structures.
• Experience designing and shipping external SDKs or partner integration APIs.
• Deep familiarity with Windows or Linux kernel architecture and driver development.
• Experience with hardware accelerator programming (GPU compute, NPU or DSP).
• Proven track record of leading technical architecture and mentoring senior engineers.

Nice-to-Have Skills Description:

• Knowledge of hardware root-of-trust, secure boot or hardware attestation mechanisms.
• Familiarity with enterprise EDR vendor integration architectures. Background in side-channel defenses or hardware security research. Experience with formally specified or safety-certified real-time systems.

Languages:

English: B2 Upper Intermediate