Formal Verification Engineer - New College Graduate
Indexed description
What You Will Be Doing
- In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
- Identify key behaviors for verification to write clear testplans for complex designs.
- Implement testplans using innovative formal techniques.
- Drive tools to realize their best performance.
- Develop flow and script to automate and improve team efficiency.
- Collaborate with other teams to help produce bug free, outstanding silicon products.
- BS/MS/Ph.D. or equivalent experience in CS/CE/EE/Mathematics
- Strong analytical and collaboration skills to solve complex problems.
- Strong coding skills in C, Perl, Python or any other industry-standard scripting languages
- Good debugging skills
- Excellent communication skills, able to effectively collaborate and work with members of a distributed team.
- Knowledge of formal verification methodologies, techniques and tools like Jasper.
- Hands-on experience with Verilog / System Verilog HDLs, SVA assertions, and able to understand complex RTL code quickly.
We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.
, , JR2008771
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