Micron Technology
Builtin · Indexed 2026-07-29
SMTS Design Verification Engineer
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Indexed description
Micron Technology SMTS Design Verification Engineer Reposted An Hour AgoSaved In-Office 5 Locations 178K-389K Annually Senior level 178K-389K Annually Senior levelArtificial Intelligence • Hardware • Information Technology • Machine LearningThe Design Verification Engineer will develop and execute verification plans, creating UVM/SystemVerilog testbenches, and ensure clean handoff from simulation to silicon.Top Skills: SystemverilogUvm
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