Sr. ASIC Design Engineer

Micron Technology Sr. ASIC Design Engineer Reposted 6 Hours AgoSaved In-Office San Jose, CA, USA 168K-336K Annually Senior level 168K-336K Annually Senior levelArtificial Intelligence • Hardware • Information Technology • Machine LearningDesign and implement digital ASIC logic across the full ASIC lifecycle: specifications, microarchitecture, RTL (SystemVerilog), simulation, synthesis, static timing analysis, timing closure, linting, CDC, and top-level integration. Leverage GenAI and agentic tools, collaborate cross-functionally, and support interfaces such as PCIe, NVMe, DRAM, NAND, and AXI.Top Skills: Agentic McpAi/LlmsApr FlowAxiCdcCpu ArchitectureDftDigital DesignDramEda Tools And FlowsGenaiLecLintingMachine LearningNandNvmePcieSimulationStatic Timing Analysis (Sta)SynthesisSystemverilogTiming Closure