Principal Design Engineer

Micron Technology Principal Design Engineer 3 Hours AgoSaved In-Office San Jose, CA, USA 176K-298K Annually Senior level 176K-298K Annually Senior levelArtificial Intelligence • Hardware • Information Technology • Machine LearningLead datapath design for NAND flash memory, focusing on TSV interface and wide parallel data buses. Drive architecture decisions, timing and signal/power integrity analysis, DFT and Verilog-based verification, post-silicon validation, and multi-team coordination to meet performance, power, and reliability goals.Top Skills: Cmos BsimDdr4Ddr5DftFull-Chip Circuit SimulationHbm3Hbm3EHbm4Lpddr4Lpddr5Lpddr6Nv-Lpddr4Parasitic ModelingPdnPower IntegritySignal IntegrityTiming AnalysisTsvVerilog