Layout Engineer, DEG

Micron Technology Layout Engineer, DEG Reposted 7 Hours AgoSaved In-Office Boise, ID, USA Mid level Mid levelArtificial Intelligence • Hardware • Information Technology • Machine LearningDesign block-level layouts using Cadence Virtuoso including floorplanning, placement, routing, and optimization. Apply physical constraints (PDN, pin placement, routing blockages), ensure DRC/LVS/density/reliability compliance, support parasitic extraction, post-layout verification, ECOs, and create partial custom layouts for device-level or small analog blocks while collaborating with cross-site teams.Top Skills: Cadence VirtuosoDramDrcEcoLvsParasitic ExtractionPdnPhysical VerificationPost-Layout Verification