Staff RTL Design Engineer
Indexed description
Arm Staff RTL Design Engineer Reposted 18 Hours AgoSaved Hybrid Austin, TX, USA 198K-268K Annually Senior level 198K-268K Annually Senior levelArtificial Intelligence • Internet of Things • SemiconductorThe RTL Design Engineer will design and analyze high-performance interconnects, ensuring they meet functional, performance, power, and area goals.Top Skills: Design CompilerGenusJasperPrimetimeRtl PowerproSystem VerilogTempusVc FormalVerilog
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