Sr. Staff Engineer, Timing Methodology & Signoff

Ambiq Sr. Staff Engineer, Timing Methodology & Signoff An Hour AgoSaved Easy Apply In-Office Austin, TX, USA Easy Apply Senior level Senior levelHardware • Internet of Things • Software • Wearables • SemiconductorLead end-to-end timing methodology and signoff for SoCs: define flows, constraints, and PVTR corners; drive block-to-SoC timing closure and pre-/post-silicon correlation; perform extraction, glitch/noise and power/timing tradeoff analysis; automate STA workflows and collaborate with RTL, DFT, PnR, IP, bring-up, and validation teams.Top Skills: CadenceCadence TempusFinfetFusion CompilerInnovusMulti-PatterningPythonStatic Timing Analysis (Sta)SynopsysSynopsys PrimetimeTcl