Technology Lead- Memory Layout

Infosys is hiring Memory Team Layout. You will work along our Registers and Memory Arrays and Memory data path layout and design engineers .Based on the schematic shared you should be able to take it forward and collaborate with circuit team etc to create best layout possible.

Required Qualifications:

• Candidate must be located within commuting distance of Burnaby BC, Canada or be willing to relocate to the area. This position may require travel in Canada.
• Bachelor's degree or foreign equivalent required from an accredited institution. Will also consider three years of progressive experience in the specialty in lieu of every year of education.
• At least 4 years of Information Technology experience.
• Candidates authorized to work for any employer in the Canada without employer-based visa sponsorship are welcome to apply. Infosys is unable to provide immigration sponsorship for this role at this time.

Required Skills

• Minimum Qualifications 5+ years of experience in Compiler/Custom Memory Layout design.
• Memory Leafcell layout library design from scratch including top level integration.
• Good knowledge on diAerent types of memory architectures.
• Good knowledge in optimized layout design for better performance.
• Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations.
• 3nm, 5 nm exposure required Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions.
• Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow.

The job may also entail sitting as well as working at a computer for extended periods of time. Candidates should be able to effectively communicate by telephone, email, and face to face.

Estimated annual compensation range for the candidate based in the below location will be:
BC- $90450 to $136500