Staff Design Verification Engineer
Indexed description
Arm Staff Design Verification Engineer 13 Hours AgoSaved Hybrid Austin, TX, USA 250K-338K Annually Senior level 250K-338K Annually Senior levelArtificial Intelligence • Internet of Things • SemiconductorThe Design Verification Engineer is responsible for the verification of memory controllers, developing testbenches, and debugging functional errors in RTL models.Top Skills: PerlPythonSystemverilogSystemverilog AssertionsUvm
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