Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)

BAE Systems, Inc. Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus) Reposted 12 Hours AgoSaved Hybrid Totowa, NJ, USA 142K-242K Annually Senior level 142K-242K Annually Senior levelAerospace • Hardware • Information Technology • Security • Software • Cybersecurity • DefenseLead planning, architecture, and development of configurable, self-checking FPGA verification environments using SystemVerilog/UVM/OVM and/or VHDL. Create constrained-random test plans, collect/analyze coverage, develop reusable VIP, mentor junior engineers, and lead small-to-medium DV teams to deliver FPGA/ASIC verification for Electronic Warfare systems.Top Skills: AsicCadenceFpgaMentor QuestaOvmSystemverilogUvmVhdl