Principal ASIC Design Engineer

We are seeking talented Principal ASIC Design Engineers with deep expertise in one or more of the critical areas needed to develop world-class SoCs for deployment in high-performance computing, advanced data analytics, and AI interconnect solutions. Ideal candidates will have relevant experience in the networking domain, with proven expertise in 50G, 100G, and 400G Ethernet protocols—including TCP/IP, RDMA/RoCE, and IPSec—and their application in high-speed data processing and networking environments.

Requirements

• Implement RTL designs using Verilog/System Verilog for high-speed data paths and packet processing logic.
• Collaborate with verification engineers to create block- and system-level test plans to ensure comprehensive design coverage.
• Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure.
• Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues.
• Contribute to performance optimization and power-aware design strategies for Host Fabric Interface subsystems.

Benefits

• Health and retirement benefits
• Medical, dental, and vision coverage
• Disability and life insurance
• Dependent care flexible spending account
• Accidental injury insurance
• Pet insurance
• Generous paid holidays
• 401(k) with company match
• Open Time Off (OTO) for regular full-time exempt employees
• Sick time
• Bonding leave
• Pregnancy disability leave

Originally posted on Himalayas