RTL Design Engineer (IP Level)
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RTL Design Engineer (IP Level)
Location :
Pan India
Experiences
4 to 12 Years
Key Skills
Synopsys Design Compiler, SpyGlass , SpyGlass CDC, Cadence Genus, JasperGold or similar
Job Description
We are seeking a highly skilled RTL Design Engineers for various RTL Design positions, to join our dynamic team. RTL design Engineers with IP level, SoC Integration and with expertise in PCIe.
Roles And Responsibilities
This is a consolidated RTL Design job description.
- Develop and implement RTL code for various IP blocks using Verilog/SystemVerilog.
- Experience with synthesis tools (e.g., Synopsys Design Compiler).
- Familiarity with linting tools (e.g., SpyGlass or similar).
- Strong understanding of CDC analysis and tools (e.g., SpyGlass CDC or similar).
- Excellent problem-solving and debugging skills.
- Strong communication and teamwork skills.
- Experience with low-power design techniques.
- Knowledge of scripting languages (e.g., Python, Tcl).
- SoC Integration experience is an added advantage.
- Strong understanding of PCIe protocol and its implementation.
- Knowledge and Experience wth Design IPS of PCIe Gen5, I2C, UCI and HBM, etc.
- Good knowledge on AMBA protocols such as APB, AHB and AXI.
Total Experiences Fresher 1 Year 2 Years 3 Years 4 Years 5 Years 6 Years 7 Years 8 Years 9 Years 10 Years 10+ Years
Relevant Experiences Fresher 1 Year 2 Years 3 Years 4 Years 5 Years 6 Years 7 Years 8 Years 9 Years 10 Years 10+ Years
Highest Qualification B.Tech B.E. Electrical M.Tech Others
Standard Notice Period 1 Month 2 Months 3 Months
Currently Serving Notice Immediate 15 Days 30 Days 45 Days 60 Days 75 Days 90 Days
we are deeply committed to the success and growth of our clients. We strive to fuel their progress by delivering high-quality engineering solutions that are innovative, reliable, and cost-effective.
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#677, 1st Floor, 13th Cross, 27th Main Rd, 1st Sector, HSR Layout, Bengaluru, Karnataka 560102
+91 6351276351
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